1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a test circuit for an ultraviolet erasable and electrically programmable non-volatile semiconductor memory.
2. Description of Related Art
At present, an electrically programmable non-volatile semiconductor memory (called "EPROM" in this specification) has been widely used. FIG. 1 shows a diagrammatic sectional view of a typical EPROM cell.
The shown EPROM cell includes a p-type semiconductor substrate 10 and a source diffused region 12 and a drain diffused region 14 formed on a principal surface of the substrate 10 separately from each other. On the principal surface of the substrate 10 between the source diffused region 12 and the drain diffused region 14, a first gate oxide 16 is formed, and then, a floating gate 18 formed of for example a polycrystalline silicon is located on the first gate oxide 16. Furthermore, a second gate oxide 20 is provided on the floating gate 18, and a control gate 22 formed of for example a polycrystalline silicon is formed on the second gate oxide 20. Therefore, the floating gate 18 is surrounded by insulators. In addition, a source electrode 24 and a drain electrode 26 are provided in contact to the source diffused region 12 and the drain diffused region 14, respectively.
In the EPROM as mentioned above, if a sufficient amount of ultraviolet light is irradiated, the EPROM is brought into an erased state in which no electric charge is accumulated at the floating gate 18. On the other hand, the EPROM cell can be put into a written state in which a number of electrons are accumulated at the floating gate 18, by applying a high voltage between the drain diffused region 14 and the control gate 22 to cause hot electrons to generate in proximity of the drain diffused region 14 and the generated hot electrons to be injected into the floating gate 18 by action of the voltage of the control gate 22. The erased state and the written state correspond to two different values in a binary notation.
The EPROM cell assume either of two characteristics shown in FIG. 2, dependently upon whether or not the electrons are accumulated in the floating gate. In FIG. 2, the axis of abscissa represents a control gate voltage, and the axis of ordinate shows a drain current flowing through the EPROM cell. As seen from FIG. 2, a threshold of the EPROM cell is low in the erased state and high in the written state. Therefore, the state of the EPROM cell can be electrically detected by applying a voltage higher than the threshold of the erased state but lower than the threshold of the written state and checking whether or not the drain current flows through the EPROM cell. This detection is ordinarily performed by a detection circuit called a "sense amplifier". Namely, data stored in the EPROM cell is read by the sense amplifier.
In general, a voltage applied to the control gate for data reading is the same as a voltage of a power supply. Therefore, if a different between the voltage applied to the control gate for data reading and the threshold voltage of the written state is not sufficient, an electric charge accumulated in the floating gate in the written state is gradually leaked out of the floating gate in use of a long term, and ultimately, a correct memory content is lost. Therefore, the EPROM is required to have a sufficient high threshold in the written state, and a sufficient insulating property of the insulator surrounding the floating gate 18 to prevent the electrons from being leaked out of the floating gate.
In other words, it is a current practice to sort or pick up only EPROMs having the above mentioned property, after the EPROMs have been manufactured. One typical picking-up method includes the steps of irradiating a sufficient amount of ultraviolet light after completion of wafer process so as to bring EPROMs in the erased state; reading the content of the EPROMs so as to confirm that the EPROMs are in the erased state; and thereafter, writing the EPROMs so as to put the EPROMs in the written state; and reading the EPROMs by applying a voltage higher than an ordinarily used power supply voltage, to the control gate of the EPROM cell, thereby examining the threshold voltage of the written state by means of a sense amplifier. The above mentioned test method for examining the written state of the EPROMs by changing the voltage of the power supply, is well known by a report "TEST ON RELIABILITY OF EPROM LSI", Japanese Electronic Parts Reliability Center.
After the EPROMs having the electrons accumulated in the floating gate are retained at a high temperature in the range of 125.degree. C. to 250.degree. C. for a period of time of one hour to 24 hours, the above mentioned test for reading the content of the EPROMs by applying a voltage higher than the power supply voltage is performed. As a result, it could be known that the threshold voltage of the written state has dropped. Namely, it is possible to remove the EPROMs in which the electrons accumulated in the floating gate has decreased as the result of the high temperature storage.
Another testing method is to set the threshold of the written state at a low level and to perform the pick-up operation by applying a not-so-high power supply voltage. The setting of the threshold of the written state at a low level can be realized by lowering the power supply voltage for writing.
Referring to FIG. 3, there is shown a block diagram of a conventional EPROM device. The shown EPROM device includes a memory cell array 30, a row decoder 32 having a plurality of output lines 34 coupled to the memory cell array 30, and a column decoder 36 having a plurality of output lines 38 coupled to a column selection circuit 40 associated to the memory array 30. The column selection circuit 40 is coupled to a read/write circuit 42. In addition, the output lines 34 of the row decoder 32 are connected to a row decoder high voltage switching circuit 44, which serves to supply a writing high voltage to a selected one of the output lines 34 of the row decoder 32. The output lines 38 of the column decoder 36 are connected to a column decoder high voltage switching circuit 46, which serves to supply a writing high voltage to a selected one of the output lines 38 of the column decoder 36.
A normal power supply voltage is supplied to the row decoder 32, the column decoder 34 and the read/write circuit 42. A first write voltage WRITE VOLTAGE 1 is supplied to the row decoder high voltage switching circuit 44, and a second write voltage WRITE VOLTAGE 2 is supplied to the column decoder high voltage switching circuit 46 and the read/write circuit 42. A third write voltage WRITE VOLTAGE 3 is supplied to the read/write circuit 42.
The normal power supply voltage and the first to third write voltages are determined on the basis of the characteristics of memory cells and a circuit construction of the EPROM device. Currently available EPROMs are such that 5 V is supplied as the normal power supply voltage from an external terminal, and 12.5 V or 21.0 V is supplied as a write voltage from an external terminal. Therefore, the first write voltage WRITE VOLTAGE 1, the second write voltage WRITE VOLTAGE 2 and the third write voltage WRITE VOLTAGE 3 are generated by voltage-converting the external write voltage of 12.5 V or 21.0 V.
In the above mentioned EPROM device, when the EPROM is written, the first write voltage WRITE VOLTAGE 1, the second write voltage WRITE VOLTAGE 2 and the third write voltage WRITE VOLTAGE 3 are used, and when the EPROM memory is read out, only the normal voltage is used. In other words, the above mentioned EPROM device cannot use a voltage sufficiently higher than the normal power supply voltage, as the normal power supply voltage for examining the change of the threshold of the EPROM while changing the power supply voltage in order to remove defects of EPROMs after the completion of wafer process.
On the other hand, variation or dispersion in manufacturing cannot be avoided in integrated circuits. Therefore, the threshold of the written state will inevitably change due to variation of a writing characteristics. In addition, the amount of change of the threshold after the high temperature storage will inevitably change due to variation of the thickness of the oxide layer surrounding the floating gate. Therefore, it is not possible to examine the written state threshold of an EPROM which has a threshold which is relatively high just after it is written and which relatively greatly drops after the high temperature storage but is still higher than the power supply voltage used for the above mentioned testing. In other words, it is not possible to sufficiently detecting the change of the written state threshold after the high temperature storage in the process of the screening. As a result, it is not possible to completely reject or eliminate defective EPROMs.